Notes to self: ICH7 - i975x - BIOS

My notes on BIOS settings for the old validation board.  Since the non-archived encrypted container I use for this sort of thing is on the system itself, it's somewhat annoying to reference when something's borked.   

Some of these are right buggers to find, and my guesses are more than likely wrong -- but I'll think of them wrongly consistently, going forward, rather than this somewhat 3 year cycle of looking them up again when I need to revisit them and have forgotten what Intel's delightful abbreviations mean.

CPU Configuration:

Max CPUID Value Limit

Determines the values that the OS can write to EAX to obtain processor information.  When enabled, the processor will limit the max CPUID input value to 0x03 when queried. Disabled, processor returns actual CPUID input value. ⁽¹⁾

GV3 Functionality

Likely EIST (Enhanced Intel SpeedStep, from Geyserville codename?) - Would be V3.2 for my Kentsfield(?) - P-State power management (in effect while processor is active) - Dynamically adjust the clock speed and automatically switch between maximum performance mode and battery-optimized mode. ⁽¹⁾

C1 Enhanced

Enhanced Processor Halt State. Reduces power consumption in idle mode (by turning off some unused parts of the processor, reducing the supply voltage and frequency) - Disable to increase overall determinism of real-time applications. (Intel: "Allows the system to change voltage level (lower) of processor when no work is being done.).

No-Execution Page Protection

Later XD Technology (?) aka Execute Disable Bit (xdbit) - Sets bounds to ban execution in areas of memory where code shouldn't be running. ⁽¹⁾

VT

Intel Virtualization Technology

PECI

Platform Environment Control Interface - Thermal Management - Allows CPU to report temperature.

Hardware Prefetcher

Tries to predict which instructions and data are required in the near future and prefetches data/code into L2 cache to reduce latency with memory reads. ⁽¹⁾

Application Processor(s)

One CPU is the Bootstrap Processor (BSP) and others are Application Processors (AP). This setting controls whether to enable the additional cores. ^{(1) (2)}

FSB Bus Park

Intel Dynamic Bus Parking(?) - Allows the chipset to shut down during inactivity to save energy. ^{(1) (2)}

IDE Config:

IDE Detect Time Out (Sec)

Amount of time to pause.

Hard Disk Write Protect

Prohibits recording on hard drives.

ATA(PI) 80Pin Cable Detection

Order of type checking for IDE cable (40pin, 80 conductor). Host & Device = checked from mobo and drive. Host = only from mobo, device = only from hdd.

SATA Link Power Management

Enable aggressive management and slumber and partial (AIPE&ASP) on all ports - Puts physical layer of link into low-power state. Potentially buggy with some linux utilities(?) ^{(1) (2)}

Stagger Spinup Support

Enabled: The BIOS will clear the staggered speed up supported bit in AHCI generic 'has capabilities' register.

Set HPCP Bit

Hot Plug Capable Port - When set to '1', indicates port's signal and power connectors are externally accessible. ⁽¹⁾

ARMD Emulation Type

ATAPI Removable Media Device - Devices which use removable media (LS-120, MO, Zip) ⁽¹⁾

SuperIO Config:

Assume PS2 Mouse Presence

Likely equivalent to PS/2 Mouse Function Control (?) - If enabled, reserves IRQ12 for PS/2 mouse.

USB Configuration:

USB Mass Storage Reset Delay

BIOS will wait [x] seconds for device to initialize.

Boot Settings Config:

AddOn ROM Display Mode

If enabled, logo screen will be followed by AddOn ROM initial screen (showing add-on card BIOS message). Keep Current - 3rd party only displayed if manufacturer set to do so; Force BIOS forces display. ⁽¹⁾

Interrupt 19 Capture

Allows host adapters to capture int 19 during boot process.

Chipset - Northbridge:

Device 2 (IGD) Enable

Device 2 (IGD) Enable - Auto: IGD enabled/disable based on GFX card detection and primary video device setup option. Disable: IGD is disabled regardless of card detection.

GMCH (Graphics Memory Controller Hub) Operating Mode

Paging modes(?) ⁽¹⁾

TOLUD (Top of Low Usable DRAM)

Contains address one byte above maximum DRAM memory below 4gb that is usable by the OS.  TOLUD is the lowest address above both Graphics Stolen memory and TSEG. BIOS determines the base of Graphics Stolen Memory by subtracting the GSM size from TOLUD and further decrements by TSEG size to determine base of TSEG. All the bits in this register are locked in Intel VT-d mode. Choices: 3.25gb / 2.75gb / 2.50gb/ 2.25gb / 2gb / 1.75gb. Note: grub doesn't like anything over 2.75gb.

Memory Reclaim

Allows reclaiming physical memory overlapped by the MMIO logical address space. MCH remaps physical memory from the TOLM boundary up the 4gb boundary to an equivalent sized logical address range located just above the top of physical memory. ⁽¹⁾

DRAM Throttling Threshold

Reduces heat; if threshold temp is exceeded, uses additional cycles; can adversely affect computer performance -- disable.

Chipset - Integrated Graphics Options:

IGD BARs Programming - ?

Device 2, Function 1

? (Related to IGD parellization?)

Chipset - South Bridge Configuration:

CPU BIST Enable

Built-In Self Test - "To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register."

SSC Enable

Spread Spectrum Clocking (?)

SLP_S4# Assertion Width

Minimum assertion width of the SLP_S4# signal to guarantee that the DRAMs have been safely power-cycled or... S4 Sleep Control: SLP_S4# is for power plane control; this signal shuts power to all non-critical systems when in the S4 (suspend to disk) or S5 (Soft Off) state. Pin must be used to control the DRAM power to use the ICH7's DRAM power-cycling feature.

80h,84-6h,88h,8C-Eh Routing

Set to LPC -- functionality for the Port 0x80 Codes(?)

LPC 4Eh-4Fh Decode

CNF2_LPC_EN - R/W - Microcontroller Enable #2

LPC 2Eh-2Fh Decode

CNF1_LPC_EN - R/W - Super I/O Enable

SPI Prefetch During Shadowing

SPI Read Configuration(?) - 00b - No prefetching, but caching enabled, 01b - No prefetching and no caching, 10b - prefetching and caching enabled, 11b - reserved. (BIOS_CNTL - BIOS Control Register)

ASF (Alert Standard Format) Management Controller Support

Allows controller to collect and send information from system components to a remote server and accept commands back from the remote console and execute on local system.

Energy Lake Support

Disables or enables Energy Lake power management technology. Introduces two main end user features: "CE" like device power behavior and maintaining system state and data integrity during power loss events. (Now known as "Intel Quick Resume Technology"?)

Intel® AMT BIOS Extension

Active Management Technology - Remote pwnage. ^{(1) (2)}

Force IDE-R (Integrated Device Electronics - Redirect) on Tekoa

Forces redirect to the network card(?)

HPET (High Precision Event Timer)

Replaces 8254 PIT and RTC.

PCIe Config:

VC1/TC Map

VC1 will be mapped to TC specified - Field indicates TCs (traffic classes) that are mapped to the VC (virtual channel) resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. (i975x reference of field this BIOS setting manipulates.) ⁽¹⁾

Remove non-POR (Power on reset(?)) TCs from VC0

Default is enabled - Removes traffic classes that don't come back after reset from virtual channel 0(??)

Lock PCIE Credits Register

Writes once to the PCIE credit register to prevent them from being modified. (src: C2D Q45 Express Chipset Development Kit)

Northbridge PCIe:

PEG Port

PCI Express Graphics port 16x - auto/disable/enable

PEG Scrambler Bypass

GFX card: BIOS forces the scrambles to be bypassed without a link disable. Enable: BIOS forces the scrambles to be bypassed by disabling and enabling the link.

PEG Retry Buffer Depth

If forced, Retry Buffer is forced to less than optimal value. (Reduces retry buffer to a lower than typically required value)

PEG Force x1

Related to Force Link Width(?) - Auto / X1 / Reserve / X4 / X8

PEG Isoch (isochronous) Flush Page

Unknown, but chipset spec has: "IFPBAR - Any write to this window will trigger a flush of the MCH's GLobal Write Buffer to let software provide coherency between writes from an isochronous agent and writes from the processor (4-kb window)" which might be related.

PEG Active State PM (power management)

Controls level of active state power management supported on the given link: 00 = Disabled, 01 = L0s Entry Supported, 10 = Reserved, 11 = L0s and LI Entry Supported. ⁽¹⁾

SERR# on Fatal (and Non-Fatal) Error

System Error is generated if (error type) is detected on the PEG port and will result in NMI (non-maskable interrupt) or SMI depending upon state of NMI to SMI setup option.

Link Stability Alogrithm

Used for verifying PCIe Link is up and running for x16 slot for x16 graphics cards.

Southbridge PCIe:

PCI Express PME (Power Management Event) SCI (System Control Interrupt) Enable

Routes PMEs through SCIs(?) ⁽¹⁾

VC1 for HD Audio - ???

Northway Training W/A - ???

Northway S4 W/A - ???

ACPI Advanced:

BIOS->AML ACPI Table

Allows update of AML. When set, the ACPI APIC table pointer is included in the RSDT pointer list.

ACPI PCI0 _S1D (S1 Device State)

The highest D-state supported by the device in the S1/S2/S3/S4 states, respectively. It should be noted that higher D-state values correspond to lower power consumption states, with D0 being the highest powered state and D5 being the lowest power state (off).

ACPI Video Extensions

Mostly for laptops(?) ^{(1 (pg 877))}

Headless Mode

Setting updates FACP (Fixed ACPI Description Table) - "System Type Attribute - If set indicates the system cannot detect the monitor or keyboard/mouse devices."

SV (Silicon Validation) Options:

Program ICH Native IDE BARs

Unknown - ⁽¹⁾

PCI Exp Bridge ISA Enable

Needs to be disabled to support DOSODI and NDIS2. Detail: "This problem appears to be related to the specific I/O address assigned to the Tekoa LAN function by the BIOS. As configured by the BIOS, I/O reads to adapter registers always fail, returning 0xFFFFFFFF. This causes the driver to be unable to read the adapter EEPROM or configure the adapter for operation and thus it fails to load."

Global SMI

CPU SMBASE relocation will not occur if set to disable.